ASSESSMENT OF THE INTEGRATED EFFICIENCY OF BLOCK CIPHER ALGORITHMS FOR WIRELESS NETWORKS ON A FPGA CHIP

Đỗ Thị Bắc; Dương Thu Mây

doi:10.34238/tnu-jst.4787

ASSESSMENT OF THE INTEGRATED EFFICIENCY OF BLOCK CIPHER ALGORITHMS FOR WIRELESS NETWORKS ON A FPGA CHIP

About this article

Received: 20/07/21 Revised: 31/08/21 Published: 31/08/21

Authors

1. Do Thi Bac, TNU – University of Information and Comunication Technology
2. Duong Thu May , TNU – University of Information and Comunication Technology

Abstract

Currently, due to the advantage of high security, high-speed block ciphers built by Controlled Substitution Permutation Network, using Switchable Data Dependent Operation, are often chosen. However, these algorithms need to be evaluated for integrated efficiency to ensure resource saving and power consumption reduction. Therefore, in this paper, in addition to introducing the block cipher algorithm BM123-128, we focus on describing how to simulate this algorithm on the XC6VLX240T Virtex-6 FPGA Chip with the support of Xillinx 14.7 software. The integrated efficiency of this algorithm has also been compared with some well-known algorithms of the same type such as EAGLE-128, CIKS-128, COBRAH128, Serpent under the same simulation conditions. Simulation results show that BM123-128 has 5 times better integration efficiency than COBRAH128 and Serpent, 2 times better than CIKS-128.

Keywords

Wireless Network Security; Controlled substitution permutation network; Switchable Data Dependent Operation; Block cipher; Field-programmable gate array

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DOI: https://doi.org/10.34238/tnu-jst.4787

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