DESIGN AND PERFORMANCE EVALUATION OF 64-BIT PRECHARGE FREE - TERNARY CONTENT ADDRESSABLE MEMORY
About this article
Received: 18/06/25                Revised: 14/11/25                Published: 18/11/25Abstract
Keywords
Full Text:
PDF (Tiếng Việt)References
[1] S. V. V. Satti, “Design of TCAM Architecture for Low Power and High Performance Applications,” GU J. Sci., vol. 32, no. 1, pp. 164-173, 2019.
[2] V. Datti and P. V. Sridevi, “Low Power High Speed Ternary Content Addressable Memory,” International Journal of Recent Technology and Engineering (IJRTE), vol. 8, no. 2, pp. 2454 - 2458, July 2019.
[3] S.Y. Doo and K. W. Kwon, “Dynamic Power Reduction in TCAM Using Advanced Selective Pre-Charging of Match Lines,” Electronics, vol. 12, 2023, Art. no. 3691.
[4] N. Sainee, R. Nigam, and S. Chouhan, “High-Density with Low-Power TCAM Design and Application,” International Research Journal of Engineering and Technology (IRJET), vol. 8, pp. 3618 - 3622, August 8, 2021.
[5] M. Zakariya and H. M. Kittur, “Precharge-Free, Low-Power Content-Addressable Memory,” IEEE Transactions On Very Large Scale Integration (VLSI), vol. 24, pp. 2614 - 2621, August 8, 2016.
[6] D. Sethi, M. Kaur, and G. Singh, Design and performance analysis of a CNFET - based TCAM cell with dual-chirality selection, Springer Science + Business Media, New York, January 27, 2017.
[7] T. V. Mahendra, S. W. Hussain, S. Mishra, and A. Dandapat, “Low discharge precharge free matchline structure for energy-efficient search using CAM,” VLSI Journal, vol. 69, pp. 31–39, 2019.
[8] G. Kumar and S. Agrawal, “Carbon Nanotube Field Effect Transistors: An Aspect of Low Power and High Frequency Applications of CNTFETs,” International Conference on Disruptive Technologies (ICDT), 2023, pp. 586-590.
[9] Y. Ahn, Y. Lee, and G. Lee, “Power and Time Efficient IP Lookup Table Design Using Partitioned TCAMs,” Circuits and Systems, vol. 4, pp. 299-303, 2013.
[10] S. Pousia and R. Manjith, “Design of Low Power High Speed SRAM Architecture using SK-LCT Technique,” IEEE International Conference on Current Trends toward Converging Technologies, 2018, pp. 1 - 7.
[11] S. V. V Satti and S. Sriadibhatla, “Dual bit control low-power dynamic content addressable memory design for IoT applications,” Turk J. Elec. Eng. & Comp. Sci., vol. 29, pp. 1274 – 1283, March 30, 2021.
DOI: https://doi.org/10.34238/tnu-jst.13084
Refbacks
- There are currently no refbacks.





