THIẾT KẾ MẠCH CDR BÁN TỐC KHÔNG SỬ DỤNG TẦN SỐ THAM CHIẾU TỪ 2.4 ĐẾN 3 Gb/s KẾT HỢP VỚI MẠCH SAN BẰNG THÍCH NGHI TRONG MÁY THU CÓ DÂY
Thông tin bài báo
Ngày nhận bài: 17/08/22                Ngày hoàn thiện: 16/09/22                Ngày đăng: 16/09/22Tóm tắt
Từ khóa
Toàn văn:
PDF (English)Tài liệu tham khảo
[1] G. Shu, W. S. Choi, S. Saxena, M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, and P. K. Hanumolu, “A 4-to-10.5Gb/s Continuous-Rate Digital Clock and Data Recovery with Automatic Frequency Acquisition,” IEEE J. Solid-State Circuits, vol. 51, no. 2, pp. 428-439, Feb. 2016.
[2] J. Jin, J. Kim, H. Kim, C. Piao, J. Choi, D. Kang, and J. Chun, "A 4.0–10.0-Gb/s Referenceless CDR with Wide-Range, Jitter-Tolerant, and Harmonic-Lock-Free Frequency Acquisition Technique," IEEE 44th European Solid State Circuits Conference (ESSCIRC), Germany, Sep. 2018.
[3] R. Inti, W. Yin, A. Elshazly, N. Sasidhar, and P. K. Hanumolu, “A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 3150-3162, Dec. 2011.
[4] J. Jin, X. Jin, J. Jung, K. Kwon, J. Kim, and J. Chun, “A 0.75–3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR With a Deadzone Compensated Frequency Detector,” IEEE J. Solid-State Circuits, vol. 53, no. 10, pp. 2994-3003, Oct. 2018.
[5] K. Sohn, T. An, Y. Moon, and J. Kang, “A 0.42 - 3.45 Gb/s Referenceless Clock and Data Recovery Circuit with Counter-based Unrestricted Frequency Acquisition,” IEEE Trans. Circuits and Systems-II, Express Briefs, vol. 67, no. 6, pp. 974-978, Jun. 2020.
[6] B. Nakhkoob and M. M. Hella, "A 4.7-Gb/s Reconfigurable CMOS Imaging Optical Receiver Utilizing Adaptive Spectrum Balancing Equalizer," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 1, pp. 182-194, 2016.
[7] D. Lee, J. Han, G. Han, and S. M. Park, "An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer," IEEE Journal of Solid-State Circuits, vol. 45, no. 12, pp. 2861-2873, 2010.
[8] H. Won, J. Y. Lee, T. Yoon, K. Han, S. Lee, J. Park, and H. Bae, "A 28-Gb/s receiver with self-contained adaptive equalization and sampling point control using stochastic sigma-tracking eye-opening monitor," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 3, pp. 664-674, 2018.
[9] Y. Lin, C. Huang, J. M. Lee, C. Chang, and S. Liu, “A 5–20 Gb/s power scalable adaptive linear equalizer using edge counting,” 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2014, pp. 273-276.
[10] Y. Choi, Y. Lee, H. Park, J. Choi, J. Sim, Y. Kwon, and C. Kim "A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS,” IEEE Trans. Circuits and Systems-II, Express Briefs, vol. 68, no. 10, pp. 3189-3193, Oct. 2021.
[11] H. Kim, and C. Joo, “A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 5, pp. 1107-1117, May 2020.
[12] G. Mandal, S. Rajan, S. K . Ghosh, S. Hazra, R. Molthati, P. R. Bhuta, S. K. Reddy, V. G. Jawarlal, and K. Pandya, “A 2.68mW/Gbps, 1.62-8.1Gb/s Receiver for Embedded DisplayPort Version1.4b to Support 14dB Channel Loss,” IEEE Asian Solid-State Circuits Conference, Japan, Nov. 2020.
[13] M. Choi, H. Ko, J. Oh, H. Joo, K. Lee, and D. Jeong, “A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler,” IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 2020.
[14] W. Rahman, D. Yoo, J. Liang, A. Sheikholeslami, H. Tamura, T. Shibasaki, and H. Yamaguchi, “A 22.5-to-32-Gb/s 3.2-pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28-nm CMOS,” IEEE J. Solid-State Circuits, vol. 52, no. 12, pp. 3517–3531, Dec. 2017.
[15] W. Chen, Y. Yao, and S. Liu, “A 10.4–16-Gb/s Reference-Less Baud-Rate Digital CDR With One-Tap DFE Using a Wide-Range FD,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 11, pp. 4566-4575, Nov. 2021.
[16] M. H. Pham, H. T. Nguyen, and T. Q. Nguyen, “An Adaptive Continuous-Time Linear Equalizer Using Sampled Data Edge Counting,” 19th International Symposium on Communications and Information Technologies (ISCIT), Ho Chi Minh City, Vietnam, Sep. 2019.
[17] H. T. Nguyen, H. Lee, T. J. An, and J. K. Kang, “A 0.32 - 2.7 Gb/s Reference-less Continuous-rate Clock and Data Recovery Circuit with Unrestricted and Fast Frequency Acquisition,” IEEE Trans. Circuits and Systems-II, Express Briefs, vol. 68, no. 7, pp. 2347-2351, July 2021.
[18] H. T. Nguyen, M. H. Pham, T. L. Le, T. T. Le, and T. Q. Nguyen, “Designing wide-band reference-less continuous-rate clock and data recovery circuit using 180 nm CMOS process,” Journal of Military Science and Technology, vol. 63, pp. 46-58, Oct. 2019.
DOI: https://doi.org/10.34238/tnu-jst.6369
Các bài báo tham chiếu
- Hiện tại không có bài báo tham chiếu