A WIDE-BAND CDR IN 28 nm CMOS PROCESS  WITH MAXIMUM FREQUENCY ACQUISITION TIME OF 0.9 μs

Nguyễn Hữu Thọ; Mai Thanh Hải; Lê Tiến Hưng; Nguyễn Thành

doi:10.34238/tnu-jst.12083

A WIDE-BAND CDR IN 28 nm CMOS PROCESS WITH MAXIMUM FREQUENCY ACQUISITION TIME OF 0.9 μs

About this article

Received: 18/02/25 Revised: 28/03/24 Published: 04/04/25

Authors

1. Nguyen Huu Tho , Le Quy Don Technical University
2. Mai Thanh Hai, Le Quy Don Technical University
3. Le Tien Hung, Le Quy Don Technical University
4. Nguyen Thanh, Le Quy Don Technical University

Abstract

This paper proposes a design of wideband referenceless half-rate clock and data recovery (CDR) circuit for high-speed serial communication applications. The proposed CDR employs a dual-loop architecture, in which the frequency acquisition loop is implemented in two-step: coarse and fine to achieve an unlimited frequency tracking range. In addition, the proposed frequency detection circuit suppresses DN_F pulses and extends UP_F pulses during frequency-increasing tracking process, while suppressing UP_F pulses and extending DN_F pulses during frequency-decreasing acquisition, thereby reducing frequency locking time in both directions. The wideband CDR circuit is designed and simulated on 28 nm CMOS technology. Simulation results demonstrate that the CDR operates effectively over a wide input data rate ranging from 1 Gb/s to 11.2 Gb/s. The CDR consumes 42.6 mW of power at input of 11.2 Gb/s with a 1 V supply. The CDR obtains a short frequency acquisition time of 0.54 μs and 0.9 μs when acquiring the maximum and minimum frequencies, respectively. The jitter performance of the recovered clock and data at 11.2 Gb/s is 1.68 ps and 1.79 ps, respectively.

Keywords

Clock anh data recovery (CDR); Wide-band; Referenceless CDR; Two-step frequency tracking; Short frequency acquisition

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DOI: https://doi.org/10.34238/tnu-jst.12083

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